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Asynchronous And Synchronous Counter

Asynchronous And Synchronous Counter


The counter is a sequential circuit that is used to count the number of clock pulses of the circuit. It is basically a digital system that counts a prescribed sequence of states upon application of input pulses. 

The input pulses (also known as count pulses) can be originated from an external source. In the counter, the sequence of states may follow a binary count either sequentially or at random. Since it produces a specified output pattern sequence, hence it is also known as a pattern generator. 

This pattern sequence might correspond to the number of occurrences of an event or it might be well to control various portions of a digital system. The counters are classified as follows

(1) Asynchronous Counter
(2) Synchronous Counter

Asynchronous Counter

An asynchronous counter is also known as a serial or ripple counter. It is simple and straightforward in operation and construction. Usually, it requires minimum hardware. In the asynchronous counter, each flip-flop except the first one is triggered by the previous flip-flop. 

In another way, the clock pulse input is applied to the only first flip-flop. The input clock pulse of the other flip-flops is the output of the preceding flip-flops. It has some speed limitations also. 

Since only the first flip-flop is directly connected to the clock signal but other flip-flops respond after some delay. So the speed of the asynchronous counter is slow. The triggering of flip-flops occurs in the ripple fashion, it is also known as ripple counter. 

The undesired output at the undesired instant (also called glitches) may occur in the asynchronous counters. The settling time of the asynchronous counter is the sum of the settling time of each flip-flop. So the settling time is more in these counters.

Synchronous Counter

The asynchronous counters are simple in construction and operation but slow in speed. If a counter with a larger number of bits is constructed, the time delay to reach the desired performance will be high. It can be avoided by constructing a counter in which all the flip-flops are triggered simultaneously by the same clock pulse. 

So the speed of the synchronous counter will be more than the asynchronous counter. There is no problem with glitches (pulses at undesired time instants) because all the flip-flops trigger simultaneously. 

The settling time of this counter will be equal to the propagation delay of a single flip-flop. Therefore, the settling time of the synchronous counter will be less than the asynchronous counter. This is also known as a parallel counter.

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