CMOS inverters (Complementary MOSFET Inverters) are some of, the “most widely used and adaptable MOSFET. inverters used in chip design. They operate with very little power loss and at relatively high speed.
Furthermore, the CMOS inverter has good logic buffer characteristics, in that, its noise margins in both low and high stakes are large. The circuit diagram of the basic CMOS inverter is shown in fig. In this circuit, CMOS inverter has two MOSFETs connected in series so that source of P-channel device Q is connected to a +ve voltage supply + VDD and the source of N-channel device Q2 is connected to the ground. Gates of both the devices are connected as common input. Drain terminals of both the devices are connected together as a common output.
+ VDD volt represents logic 1 and 0 volt represents logic 0. Now consider the first case when the input is kept at low level i.e., at 0 volts, the gate of MOSFET Q is at-ve potential relative to the source. So Qi will be on with its resistance Ronlk2, while the gate of Q2 will be at zero potential relatives to its source So Q2 will be off with its resistance Roff-1010Ω. Both of these resistances act like a potential divider and output of this will be approximately + VDD volts.
In other case, when input is kept at high level i.e. at +VDD volts, the gate of MOSFET Q is at zero potential relative to its source so Qi will be off with its resistance R,,-1010(2 while gate of Q2 will be at +ve potential relative to its source so Q2 will be on with its resistance Ron 1 k2. In this case, the output will be approximately 0 volts. Thus circuit shown in fig. acts as an inverter.